1. Field
Various embodiments relate to a memory cell array and a nonvolatile memory device, and more particularly, to a memory cell array having a sense amplifier per sub-memory bank, and a nonvolatile memory device including the memory cell array.
2. Description of the Related Art
Semiconductor memory devices may be generally divided into volatile memory devices and non-volatile memory devices. The volatile memory devices store data by utilizing logic states of bi-stable flip-flops, or by charging or discharging capacitors. The volatile memory devices lose stored data when power is turned off.
The non-volatile memory devices, such as flash memory devices, retain stored data over time, even when power is turned off. The non-volatile memory devices are used to store data or programs in a wide range of applications and devices, such as computers, mobile communication devices, etc. Since flash memory devices, in particular, are capable of electrically erasing/writing data, flash memory devices are widely used in applications requiring continuous updates. For example, flash memory devices may be used as storage devices storing system programs.
FIG. 1 is a block diagram illustrating a portion of a memory cell array 10 included in a conventional flash memory device. Generally, a memory cell array may include multiple sub-memory banks. In FIG. 1, the memory cell array 10 is illustrated as having two sub-memory banks for the sake of description.
Referring to FIG. 1, the memory cell array 10 includes a first sub-memory bank 12, a second sub-memory bank 14 and a sense amplifier 16. The first sub-memory bank 12 and the second sub-memory bank 14 constitute one memory bank.
The first sub-memory bank 12 includes first sectors S1, S2, S3 and S4, and the second sub-memory bank 14 includes second sectors S5, S6, S7 and S8. The first sectors S1, S2, S3 and S4 are coupled to the sense amplifier 16 through a first global bit line GBL, and the second sectors S5, S6, S7 and S8 are coupled to the sense amplifier 16 through a second global bit line GBR. The sense amplifier 16 senses and amplifies signals output from the first and second sectors S1, S2, S3, S4, S5, S6, S7 and S8, and provides the amplified signal through an input/output line IOL.
In the conventional memory cell array 10, the sense amplifier 16 may not be located in the middle of the first sub-memory bank 12 and the second sub-memory bank 14, but rather may be located off to one side, due to the existence of circuit blocks, such as a bank driver. Therefore, a coupling characteristic of the conventional memory cell array 10 may be deteriorated since an output signal of the first sub-memory bank 12 and an output signal of the second sub-memory bank 14 are amplified by the same sense amplifier 16 and output through the same input/output line IOL.
To improve the coupling characteristic, a conventional memory cell array may have the same number of sense amplifiers as sub-memory banks, so that the sub-memory banks constituting one memory bank do not share the input/output line IOL. Thus, the sub-memory banks constituting one memory bank are accessed by separate input/output lines and separate sense amplifiers, thereby improving the coupling characteristic. However, in order for a flash memory device to have the same number of sense amplifiers as sub-memory banks, the conventional flash memory device must have a large circuit size. Moreover, in the conventional flash memory device, power noise is increased.